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Phase-guided Thread-to-core Assignment for Improved Utilization of Performance-Asymmetric Multi-Core Processors


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Sondag, Tyler and Rajan, Hridesh (2009) Phase-guided Thread-to-core Assignment for Improved Utilization of Performance-Asymmetric Multi-Core Processors. Technical Report 08-14, Computer Science, Iowa State University.

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Abstract

CPU vendors are starting to explore trade offs between die size, number of cores on a die, and power consumption leading to performance asymmetry among cores on a single chip. For efficient utilization of these performance-asymmetric multi-core processors, application threads must be assigned to cores such that the resource needs of a thread closely matches resource availability at the assigned core. This significantly complicates the task of an average programmer. The contribution of this work is a technique for automatically determining the mapping between threads and performance-asymmetric cores of a processor. Our approach, which we call phase-guided thread-to-core assignment, builds on a well-known insight that programs exhibit phase behavior. We first take code sections and group them into clusters such that each section in a cluster is likely to exhibit similar runtime characteristics. The key idea is that with this clustering, characteristics of a small number of representative sections in the cluster give insight into the behavior of the entire cluster. Thus the exhibited characteristics of the representative sections on different types of cores can be used for automating thread-to-core assignment at a lower runtime cost. Variations of our technique show more than 100% improvement in throughput over the stock Linux scheduler for systems with a constant feed of jobs, while maintaining comparable fairness and efficiency. No modifications to existing compilers or underlying operating systems is necessary, facilitating transparent deployment. Furthermore, our framework implementing this strategy produces standalone binaries that are independent of the characteristics of the target performance-asymmetric multi-core architecture thus avoiding the need to create multiple customizations of the binary.

Keywords:static program analysis, heterogeneous multi-core processors, thread-to-core assignment, phase behavior
Subjects:Software: SOFTWARE ENGINEERING (K.6.3): Coding Tools and Techniques
Software: PROGRAMMING LANGUAGES: Processors
Software: OPERATING SYSTEMS (C): Performance (C.4, D.2.8, I.6)
ID code:00000592
Deposited by:Tyler Sondag

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